1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to an electrically erasable programmable read only memory (EEPROM) and a method for manufacturing an EEPROM.
2. Discussion of the Related Art
As kinds of non-volatile memories, there are, e.g., a single-poly electrically erasable programmable read only memory (EEPROM) having a single poly-crystalline silicon (polysilicon) layer acting as a gate, a stacked gate (EEPROM tunnel oxide [ETOX]) non-volatile memory (NVM) having two poly-crystalline silicon layers vertically stacked one above another, a dual-poly EEPROM between the single-poly EEPROM and the stacked gate, and a split gate EEPROM.
Generally, although the stacked gate has the smallest cell size and complex circuitry and thus, is suitable for high density or high performance applications, recommending the stacked gate for low density NVM applications may be inappropriate. EEPROM is an advantageous NVM for use in the low density applications. For example, the single-poly EEPROM may be manufactured by adding approximately two mask processes to an otherwise standard process for manufacturing semiconductor logic devices.
Hereinafter, a general EEPROM will be described.
FIG. 1 is a plan or layout view illustrating a general EEPROM cell.
The general EEPROM cell shown in FIG. 1 performs a programming operation and an erase operation by Fowler-Nordheim (F-N) tunneling. A tunneling region 50, a read transistor region 52, and a control gate region 54 shown in FIG. 1 will be described in detail in the following detailed description. The respective regions 50, 52, and 54 include active regions 20A, 20B, and 20C, and wells 10A, 30, and 10B. A patterned polysilicon layer 40 is formed in part over the regions 50, 52 and 54.
In the EEPROM cell shown in FIG. 1, assuming the use of an N-type metal oxide semiconductor (NMOS) transistor, both the wells 10A and 10B are N-type, whereas the well 30 is P-type. In this case, it is necessary to isolate at least part of the EEPROM cell from a P-type semiconductor substrate (see FIG. 2).
Meanwhile, to perform the programming and erase operations, the tunneling of electrons occurs in the tunneling region 50. An efficiency of these operations generally depends on a coupling ratio between a capacitance A of the tunneling region 50 and a capacitance B of the control gate region 54.
To increase the coupling ratio between the two capacitances A and B during the programming and erase operations, an area of the control gate region 54 should be increased to increase an overlap area between the active region 20C and the patterned polysilicon layer 40 in the control gate region 54. However, this increase in overlap may increase the entire size of the cell. As a result, an EEPROM containing a relatively small number of bits (e.g., several tens of bits) may have an increased cell area and consequently, deteriorated (or at least partially inefficient) cell density.
Although it may be suggested to manufacture a dual-poly EEPROM cell in order to achieve enhanced cell density, a dual-poly EEPROM manufacturing process may require a separate process for forming the dielectric layer between the control gate and the floating gate (e.g., for controlling the capacitance between the gates), or a separate process for forming the control gate, resulting in a relatively complicated manufacturing process of the EEPROM cell.